(Phys.org)—Toshiba has announced a low-power embedded SRAM memory chip which may make future mobile devices last longer. Presenting its SRAM developments at the International Solid-State Circuit Conference in San Francisco in February, Toshiba said that its low-power design technique could help cut active and standby power consumption by 27 percent and 85 percent, respectively. Toshiba accomplished this by using a bit-line power calculator, or BLPC, to predict the power consumption of the bit lines and to monitor consumption of SRAM rest circuits, and a digitally-controllable retention circuit, or DCRC. …read more
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